1. Field of the Invention
The present invention relates to integrated circuit non-volatile memory devices, and more particularly to a novel memory cell and operating method for such device.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies known as EEPROM and flash memory based on charge storage are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising in memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, MONOS and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
FIG. 1 is a simplified diagram of a prior art SONOS-type charge trapping memory cell. The substrate includes n+-doped regions that act as source and drain terminals 15 and 16, and a p-doped channel region 17 between the terminals 15 and 16. The remainder of the memory cell includes a charge trapping structure including bottom dielectric 14 on the substrate, a charge trapping material 13 on the bottom dielectric 14, a top dielectric 12 on the charge trapping material 13, and a gate 11 on the top dielectric 12. Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al2O3. Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping materials for this type of charge trapping structure include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including silicon oxynitride, metal oxides such as Al2O3, HfO2, and others. The charge trapping material may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawings.
The terminals 15, 16 for the memory cell act as source and drain in the bias arrangements used for reading, programming and erasing the memory cells. The doped regions, forming terminals 15, 16, typically comprise impurities that are implanted into the semiconductor substrate to establish conductive terminals having a conductivity type which is the opposite of that in the channel region 17. The procedures for implanting the impurities that result in diffusion of the implanted impurities into the semiconductor substrate can limit the ability to shrink the length of the channel between the terminals 15 and 16, even as the minimum dimensions achievable using lithography shrink.
FIG. 2A and FIG. 2B illustrate one bias arrangement in the prior art that induces Fowler-Nordheim tunneling from the substrate into the charge trapping structure, for programming a memory cell to a high threshold state. FIG. 2A is a table showing the bias voltages on the gate Vg, source Vs, drain Vd and substrate Vb, which result in electron tunneling as illustrated in FIG. 2B, according to this prior art arrangement.
FIG. 3 shows prior art SONOS-type cells arranged in series for a NAND-type array structure, with a bias arrangement illustrated for programming a selected cell. The series of cells in FIG. 3 comprises n+ doped regions 20–26, select gates SLG1 and SLG2, and word lines WL1–WL4. Charge storage structures 27–30 are provided beneath the word lines WL1–WL4, and over channel regions 31–34 between the doped regions 21 and 22, doped regions 22 and 23, doped regions 23 and 24, and doped regions 24 and 25 respectively. Doped regions 20 and 26 act as bit lines or contacts for bit lines BL1 and BL2, respectively. The select transistors formed by the select gates SLG1 and SLG2, doped regions 20 and 21, and doped regions 25 and 26, respectively, act to connect the series of memory cells to, or isolate the series of memory cells from, the bit lines BL1 and BL2. In order to program a selected memory cell in the series, such as the memory cell at WL1, a bias arrangement is applied as illustrated in which BL1 is coupled either to ground (to program the selected cell by FN injection) or to a supply potential Vcc (to inhibit programming of the selected cell). The select gate SLG1 receives the supply potential Vcc in order to couple the bit line BL1 to the doped region 21. The select gate SLG2 receives zero volts or ground in order to isolate the bit line BL2 from the doped region 25. The word line of the selected cell, WL1 in this example, receives a high-voltage of about 18V, while the substrate is grounded. The word lines of unselected cells receive a voltage of about 10V, which is sufficient to induce inversion in their respective channel regions, but insufficient to cause significant charge injection. As shown in FIG. 3, a doped region is formed between each channel region.
Thus, one limitation on the size of traditional memory cells arises from the use of diffusion lines in semiconductor substrates for source and drain terminals. The diffusion of impurities used to form the diffusion lines spreads out beyond the locations in which the implant is made, increasing the size of the doped region and causing other limitations on cell size, including minimum channel lengths for prevention of punch-through.
One approach to overcoming the problems with use of diffusion lines has been developed based on inducing conductive inversion regions in the substrate using control electrodes adjacent to the charge storage structure in the memory cell, so that the dynamically established inversion regions act as source and drain terminals. Because there are no implants, the dimensions of the inversion regions can be more precisely controlled according to the minimum feature sizes of the manufacturing process. See, Sasago et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2F2/bit and programming throughput of 10 MB/s,” IEDM, 2003, pages 823–826 and United States Patent Application Publication No. U.S. 2004/0084714 by Ishii et al. The assist gate technique of Sasago et al. might be considered an extension of so called “split gate” technology applied to floating gate memory devices in a variety of forms. See, U.S. Pat. No. 5,408,115 by Chang for background related to split gate devices.
It is desirable to provide memory technology for nonvolatile memory that is easily manufactured and supports high-density applications.